Hot Chips 2026: Intel dives deep on Crescent Island AI accelerator — larger caches and deeper XMX engines target maximum AI FLOPS per watt

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Intel shared more details of its Crescent Island AI accelerator, powered by the Xe3P architecture, at the Hot Chips symposium this week. Unlike Nvidia’s Rubin and AMD’s MI455X GPUs, which are high-power, exclusively liquid-cooled chips with massive pools of HBM4 memory that provide maximum performance across both AI training and inference workloads, Crescent Island is designed to fit into a lower-power, inference-first niche in the AI accelerator market.

As a refresher, Crescent Island is a 350W air-cooled PCIe card that uses up to 480 GB of LPDDR5X memory, meaning it can be deployed in traditional servers without exotic power and cooling requirements. We’ve already learned about some of Crescent Island’s DNA from past disclosures, but Intel went deeper into the chip’s architectural details at Hot Chips.

Crescent Island is built up from four Xe3P slices, each containing eight Xe Cores, for a total of 32. Each Xe Core has eight Xe Vector Engines and eight XMX matrix accelerators, for a total of 256 of each resource.

The Xe3 graphics architecture, as seen on Intel’s Panther Lake processors, already modified the capacity and flexibility of the GPU cache hierarchy to improve utilization and decrease performance-sapping register spills, and Xe3P further refines that hierarchy.

The Xe3P Xe Core has twice the amount of general register file space for working data versus Battlemage. Each Xe Core now has 1MB of general-purpose register file space, up from 512KB on Battlemage and Xe2. In addition, Xe3P offers 512KB of L1 cache or shared local memory per Xe Core, a structure that started out at 256KB on Battlemage and grew by approximately 1.33x on Panther Lake’s Xe3 GPU. The chip also has 32MB of shared L2 cache. These expanded caches are meant to serve the chip’s larger matrix accelerators on its AI compute-focused mission.

Xe3P boasts a larger systolic depth in its XMX engines than past Xe GPU designs. Xe3P’s XMX systolic engines are a 16-deep design, meaning they can process matrices in much larger chunks than the four-deep systolic design of Xe2 and Xe3. Nvidia doesn’t discuss the architecture of its Tensor Cores in anywhere near this level of detail, but as an AI inference-focused part, the fact that Xe3P can theoretically work on more elements at once during general matrix-multiply operations is an important capability boost for Crescent Island’s inference ambitions.

Intel is also prioritizing a broad range of data types with this chip, from FP4 formats with microscaling support (aka MXFP4) all the way to what it describes as full-rate double-precision (via 64 FP64 FMA units per Xe Core). FP64 isn’t widely used in AI workloads, but Intel says that the inclusion of full-rate processing for that data type makes Crescent Island useful as a converged high-performance computing and AI chip.

Each Xe Core also supports sigmoid and tanh transcendental functions, which are important to a variety of operations during AI inference, especially the softmax function. AMD and Nvidia have prioritized the performance of these functions in their recent architectures as well, so the fact that Xe3P offers support for them is key for its AI-first initiatives.

While Crescent Island does have a media codec block featuring four encoders and decoders to help serve up video to multimodal AI models, gamers hoping for a glimpse of future Arc cards won’t find it with this product, as graphics-specific functionality like RT cores has been omitted from this chip to preserve die area for compute functionality.

As a data-center-focused part, Crescent Island offers a full suite of reliability, availability, and serviceability features, including ECC and parity protection across the die and a range of memory reliability features.

As for the specific applications that Crescent Island will target, Intel highlights the rise of mixture-of-experts models paired with speculative decoding as a new class of workload that Crescent Island can serve well.

Speculative decoding strategies vary, but in general, they use a fast, lightweight mechanism to create drafts of future tokens that the main model can then be used to accept or reject, potentially improving decode performance. Not every draft token generated this way will be approved, but much like speculative execution in CPUs, it helps produce useful work from compute resources that would otherwise be left idle.

As model serving recipes pursue more aggressive drafting mechanisms, more compute is required to generate those draft tokens. At a high level, that understanding changes the common perception of decode as being a mostly memory-bandwidth-bound operation.

As an LPDDR5X-powered chip, Crescent Island won’t have the eye-popping bandwidth of HBM-backed accelerators at its disposal for maximum performance with traditional autoregressive decode, so any help it can get from these speculative methods will be helpful.

Overall, Intel claims that Crescent Island is built to offer high FLOPS per watt and that it’s optimized for compute-bound workloads like prefill (aka prompt processing and KV cache construction). Intel’s emphasis on those areas of AI performance, as well as heterogeneous deployments, suggests that this chip could have a niche alongside HBM-backed accelerators whose resources are best used for decode operations.

Intel and its partner SambaNova could both stand to benefit from such an arrangement, as that company’s SN50 inference accelerators are explicitly built to benefit from disaggregated prefill processing powered by GPUs. SN50 racks and Crescent Island are both meant to serve as lower-power, air-cooled systems that customers can deploy in existing data centers without dramatic upgrades to power or cooling infrastructure, so there is broad synergy in the shape of those products.

Intel still isn’t discussing just how many theoretical compute FLOPS to expect from Crescent Island, nor is it disclosing memory bandwidth figures. But the architectural decisions it’s shared so far — getting lots of data close to the compute engines of the chip and processing more of it at once in a relatively narrow power envelope — seem sound in a world where the company is still trying to reset its AI ambitions after a string of high-profile product failures and cancellations.

Intel has promised Crescent Island for a second-half 2026 time frame, and the clock is ticking on that launch window, so we’re eager to learn more about the chip’s final specifications, as well as customer and partner wins, when that launch does occur.