The current state of PCIe 6.0 SSDs and controllers — Marvell, Phison, and SMI prepare controllers as drives finally come to market following years of delays

The PCIe 6.0 specification was ratified in early 2022, but its actual implementation was delayed for years. Now, the spec is almost ready, with the first PCIe Gen6 platforms finally approaching, as are actual storage devices. Micron was the first with a PCIe 6 SSD in mid-2025, and Samsung caught up this July. Meanwhile, independent makers of SSD controllers — Marvell, Phison, and Silicon Motion — are also prepping their PCIe 6 SSD platforms.

For a full roadmap of PCIe, you can check out our dedicated page. In this article, we’ll specifically focus on PCIe 6.0 controllers and devices and how they’re soon becoming commercial products. For additional reading, you can also find our interview with Solidigm VP Avi Shetty, which covers the subject of PCIe 6.0 SSDs.

Per ardua ad astra

PCIe 1.0 through 5.0 used simple NRZ signaling (one bit per signal) with 128b/130b encoding, which was relatively simple to implement at the controller level. However, it required some complicated methods to ensure signal integrity at 32 GT/s per lane.

PCIe 6.0 now adopts PAM4 signaling (which encodes two bits per symbol using four voltage levels), which keeps the physical signaling rate at 32 Gbaud. However, it also doubles the effective transfer rate to 64 GT/s by transmitting two bits per signal instead of one. As a result, transmitter and receiver design became considerably more complicated, as it required sophisticated DSPs, equalization, FEC, and CRC-based retry mechanisms, which complicated the development of PCIe 6.0 controllers. Furthermore, PCIe 6.0 often requires retimers where PCIe 5.0 did not, which complicated the development of actual servers.

To make matters even more complicated, every new PCIe generation requires interoperability testing among CPUs, GPUs, SSDs, network cards, switches, retimers, and other devices from dozens of vendors. Since PAM4 behaves very differently from NRZ, PCI-SIG had to develop entirely new compliance procedures, test equipment, and interoperability programs. The development of those programs themselves slipped, which greatly delayed any commercial deployment. The very first PCIe 6 interoperability testing at 64 GT/s took place in late July.

Despite formidable implementation hurdles and interoperability program challenges, PCIe 6 is finally making its way into commercial platforms. AMD’s 6^th Generation EPYC ‘Venice’ and Nvidia’s Vera CPUs fully support PCIe Gen6, so companies from the adjacent industry sectors are catching up with their PCIe 6 products, and storage makers are among them.

For storage, PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link without the protocol’s overhead (which is not that big with the 1b/1b 242B/256B FLIT encoding featured by PCIe 6). The new interconnect does not improve flash operation on its own. Meanwhile, PAM4 introduces Forward Error Correction (FEC), which slightly increases latency, but it also enables doubling throughput without doubling the signaling frequency to 64 Gbaud.

As a result, PCIe Gen6 generally delivers better bandwidth-per-watt than what an equivalent 64 Gbaud Non-Return-to-Zero (NRZ) implementation would have required. Given that modern data center deployments (particularly for AI) tend to be large, a greater bandwidth-per-watt metric should always be welcome.

In this story, we will summarize what the first breed of merchant enterprise-grade PCIe Gen6 controllers from three popular vendors will offer, and what we already have on the market from Micron and Samsung.

Marvell Bravera SC6: 500TB or more of speedy storage

Matt Murphy’s appointment as Marvell CEO in 2016 marked one of the most dramatic strategic shifts in the semiconductor industry. Marvell transitioned from being a large merchant chip supplier to a company almost exclusively focused on data infrastructure, and that transformation had significant implications for its storage controller business. Storage still complements the broad data-center portfolio alongside networking, custom silicon, switching, compute, and optical connectivity. However, gone are the days when storage was a major priority for Marvell. Yet, Marvell’s Bravera SC6 (MV-SF1410) looks to be quite a significant contender for the PCIe 6 storage market.

The Bravera SC6 controller is powered by 15 Arm cores in total, including 12 Cortex-R82 cores arranged in two six-core clusters, three Cortex-M7 cores, and a dedicated Cortex-M3 secure processor. The controller is NVMe 2.2 compliant and features a PCIe 6.0 x4 host interface, thus potentially offering a maximum of 30.25 GB/s of throughput.

The MV-SF1410 controller features 16 NAND channels, eight chip enables (CE) per channel, and support for SLC, MLC, TLC, and QLC 3D NAND with an up to 3600 MT/s interface. The part also supports Marvell’s sixth-generation NANDEdge technology with LDPC error correction, a hardware RAID engine, end-to-end data protection, 5 MB of SRAM, and a 64-bit DDR5 interface with ECC. The security subsystem of the Bravera SC6 supports AES, SHA, RSA, and elliptic-curve cryptography (which seems to be among the industry’s firsts), enabling compliance with Trusted Computing Group (TCG) security standards.

One of the things that strikes the eye about the Bravera SC6 is that its interfaces support data transfer rates of up to 3600 MT/s. While this speed bin seems a bit outdated now that 4800 MT/s devices have been announced, in eight- or 16-channel configurations, a 3600 MT/s transfer rate with raw bandwidth of around 3.6 GB/s per channel (38.8 GB/s and 57.6 GB/s in total, respectively) is more than enough to saturate a PCIe 6.0 x4 interface (30.25 GB/s without the overhead).

Another notable thing is that Marvell has not publicly disclosed the controller’s maximum addressable NAND capacity or logical unit number (LUN) it can support within each CE, so we cannot derive an actual maximum addressable capacity or maximum usable capacity from the public specification we have at hand*. But we can make some useful estimates. The SC6 has 16 NAND channels and eight chip enables per channel, or up to 128 CE positions in total.

With upcoming 2 Tb 3D QLC NAND dies, each die stores 256 GB. Kioxia/Sandisk formally announced such devices last week, but did not disclose their availability timeframe. Since BiCS10 is aimed specifically at data center applications, Kioxia has indeed described this generation as suitable for very highly stacked packages, without disclosing the maximum number of NAND devices per package. Typical NAND packages carry between 1 and 16 NAND devices (though Kioxia/Sandisk probably meant more than 16 devices), though packages aimed at high-capacity drives tend to feature 8 or 16 devices. 16 2-Tb devices give 32Tb (or 4 TB) per NAND package.

If an SC6 implementation could populate 128 such package positions, that gives 512 TB of raw NAND memory. Of course, actual drives will have to reserve plenty of NAND for overprovisioning and other techniques required for reliability and longevity, so actual commercial SSDs will offer a lower capacity. However, they will remain in a 500TB-class. Meanwhile, if the SC6 can address 32-die packages, then we are talking about petabyte-class SSDs. Yet, 32-die NAND packages may require something other than formal controller support.

Marvell says that it will start sampling its Bravera SC6 (MV-SF1410) with its partners sometime in Q4 2026, which means that the first drives featuring the chip will hit the market in late 2027, but more likely in 2028. Given that actual SSDs featuring the controller are so far away, Marvell even refrained from disclosing the expected performance of these products and only told us to expect “multi-gigabyte-per-second throughput, millions of random IOPS, deep queue parallelism, and highly efficient DMA-based data movement.”

*A CE may select a package containing many dies, and each die may contain multiple LUNs. To address all those dies and LUNs efficiently, the controller must be architected appropriately. If the number of supported LUNs is lower than the number of LUNs featured by all-flash devices in all-flash packages, this will affect performance and parallelism, which will lower the appeal of such drives for data center operators.

Phison X3: Up to 2PB of storage at 28.8 GB/s

Phison has yet to make a big formal announcement of its X3 — aka PS5303 — SSD controller, but it was demoed at both CES and Computex this year. At CES, the company only showcased concepts of its PCIe Gen6-based drives, whereas at Computex it showed off reference drives, clearly suggesting that it is in the final stages of development.

The Phison X3 (PS5303) is the company’s first-generation PCIe 6.0 x4 enterprise SSD controller, and it happens to be specifically aimed at data center applications, which include AI, cloud, and hyperscale deployments. Normally, Phison would introduce an eight-channel controller that would target both high-end desktop, workstation, and server applications. But such controllers have not yet surfaced.

The X3 is a 16-channel and NVMe 2.3-compliant controller, which Phison rates for up to 28 GB/s sequential read and write performance, 6.8 million random read and write IOPS, and approximately 4 GB/s per watt, which doubles the performance and efficiency of the company’s PCIe 5.0 enterprise controller. Keeping in mind that its current-generation controller is made on TSMC’s N12 manufacturing technology, whereas the X3 is produced on the N4 fabrication process, this improvement is expected.

Perhaps the most intriguing specification is support for SSD capacities of up to 2 Petabytes, which likely suggests that the controller has been designed with multiple future generations of dense 3D NAND flash memory in mind.

The controller supports OCP Datacenter NVMe SSD Specification v2.6, advanced enterprise security features including TCG Opal 2.3, DOE, IDE, Caliptra, and CNSA 2.0, as well as 64 SR-IOV physical functions for storage virtualization.

Phison has indicated that reference designs — E3.S, E1.S, etc. — are expected to sample this November, while volume production is anticipated in 2027, if everything proceeds in accordance with the plan. If the company succeeds, the X3 (PS5303) will be one of the first merchant PCIe 6.0 SSD platforms intended for next-generation storage infrastructure in 2027. Then again, it usually takes a year before sampling and availability of the actual drives.

Silicon Motion’s SM8466: A mystery at 28 GB/s

Silicon Motion was probably the first company to reveal many of its details about its PCIe Gen6 plans in an interview with Tom’s Hardware in June ’25, then a leak with some details about its PCIe 6.x SSD controller emerged in July ’25. After then, SMI kept it pretty much close to the chest about the SM8466 unit, but let us recall what we know about the controller both from our interviews and from the leaks.

Silicon Motion’s MonTitan SM8466 is the company’s 2nd-generation enterprise-grade controller that is projected to support 16 NAND channels, next-generation TLC and QLC 3D NAND, NVMe 2.x, OCP enterprise SSD specifications, and enterprise security technologies such as TCG Opal, Secure Boot, and SR-IOV virtualization, based on our interviews with the company as well as leaks.

Just like its direct rival from Phison, the SM8466 is rumored to offer 28 GB/s of sequential throughput and 7 million random IOPS, though no official claims have been made so far. Just like the Marvell controller, the SM8466 supports SCA and other features of modern enterprise-grade SSD platforms.

Perhaps the most surprising part of the specification is support for SSD capacities of up to 512 TB, which clearly falls short of the 2 PB capacity advertised by Phison’s competing PCIe 6.0 controller. Then again, this is based on leaks and rumors, rather than official information.

Now that we know something about PCIe Gen6 SSD platforms from Marvell, Phison, and Silicon, let us recall what is already on the market, or about to hit it.

Micron’s 9650: First and furious

Micron’s 9650 is the industry’s first PCIe 6.0 x4 SSD that is based on an in-house controller and the company’s 276-layer G9 3D TLC NAND with a 3600 MT/s interface. The drive delivers up to 28 GB/s sequential reads, 14 GB/s sequential writes, 5.5 million random read IOPS, and 900,000 random write IOPS. Depending on the exact SKU, the drive offers up to 25.6 TB of storage.

Since the 9650 is aimed purely at AI servers based on Nvidia hardware, Micron has optimized the SSD for peer-to-peer PCIe 6.0 communication with Nvidia Blackwell GPUs using retimers and switches to enable storage to feed accelerators without CPU involvement.

Micron started sampling its 9650 back in Q3 2025, so by now this drive is likely already available to interested parties.

Samsung’s PM1763: 16 TB at 28 GB/s

Samsung has never announced sampling of its first-gen PCIe 6.0 x4 SSD, but it officially began mass production of its PM1763 drive this July. The PM1763 drive is based on a proprietary controller made using Samsung Foundry’s 4nm-class fabrication technology as well as Samsung’s ninth-generation V-NAND.

When it comes to capacity, the PM1763 is offered in 4TB, 8TB, and 16TB capacities. The flagship 16 TB model delivers up to 28.4 GB/s sequential read and 21.9 GB/s sequential write speeds, though the company hasn’t disclosed the random performance of either SSD. Then again, to maximize performance, the drive’s design is optimized for direct-to-chip (D2C) liquid-cooled servers (Samsung has not divulged details, though).

When it comes to power efficiency, Samsung claims the drive delivers more than 1.8X higher power efficiency than its predecessor and enables it to sustain peak performance during prolonged AI training and inference workloads. Unfortunately, without hard numbers, we can only take Samsung at its word.

In addition, the SSD supports post-quantum cryptography (PQC) algorithms to help protect against future quantum computing attacks, as well as the TEE Device Interface Security Protocol (TDISP) to secure data movement in virtualized server environments.

According to Samsung, the PM1763 has completed validation for next-generation AI platforms and is positioned as a storage solution for an AI data center near you.

Almost across the line

After years of delays caused by the transition to PAM4 signaling and the resulting ecosystem-wide validation effort, PCIe 6-class storage is finally approaching commercialization.

While Micron and Samsung already offer PCIe 6.0 SSDs, merchant controller suppliers —Marvell, Phison, and Silicon Motion — are prepping their next-generation enterprise platforms with up to 16 NAND channels, throughput approaching 28–30 GB/s, and support for capacities ranging from 512 TB to as much as 2 PB.