TSMC confirms significant yield and performance improvements in A14 update — strong interest from AI/HPC and smartphone customers

TSMC’s A14 (1.4nm-class) fabrication process has made rapid progress in the last three months and is well ahead of N2 at the same stage of development, according to the company’s update provided at its earnings call this week. The technology also faces strong customer interest and engagement across both smartphone and AI/HPC applications.

“A14 technology development is on track and progressing well. Internal product-like vehicle demonstrated close to 90% device performance and close to 90% 256Mb SRAM yield,” said C.C. Wei, chief executive of TSMC, during the earnings call with analysts and investors.

A14 — which is expected to enter mass production in 2H 2028 — is making rapid progress in terms of performance and yield improvements. This April, the company disclosed that the production node achieved >85% target transistor performance and >80% 256Mb SRAM yield. Roughly three months later, both figures are approaching 90%, which suggests a gain of around 5% in device performance and nearly 10% in SRAM yield.

For comparison, TSMC’s N2 demonstrated more than 80% of its target device performance and over 50% yield on a 256Mb SRAM test chip in April 2023. By April 2024, the process had advanced to more than 90% of its target device performance and over 80% SRAM yield. While development trajectories are not directly comparable, the figures suggest that A14 is maturing considerably faster than N2 did at a similar stage of development.

The very rapid progress of A14 compared to the relatively slow maturation of N2 at similar stages of development can probably be attributed, at least in part, to TSMC’s growing experience with gate-all-around (GAA) nanosheet transistors. Back in 2023, the company barely had enough experience with the production of gate-all-around (GAA) nanosheet transistors, as N2 is its first process technology to adopt such a structure. By contrast, A14 relies on TSMC’s 2nd Generation of GAA devices, so it can probably benefit from the transistor-design improvements, process refinements, and manufacturing expertise accumulated during the development and ramp of N2.

It appears TSMC has likely eliminated many of the yield limiters with A14 and N2, though keep in mind that a high 256Mb SRAM yield merely indicates low enough defect density and good process uniformity across a highly repetitive test structure, but it is not directly representative of functional or parametric yield of a commercial processor.

Nonetheless, the close to 90% device performance and close to 90% 256Mb SRAM yield about 2.5 years away from expected mass production start put TSMC’s A14 progress well ahead of N2. Such progress can potentially enable TSMC to start high-volume manufacturing (HVM) using A14 ahead of schedule, provided that customer designs are ready, or initiate HVM with better-than-usual functional and parametric yields.

Speaking of customer design readiness, Wei indicated that clients strive to tape-out their A14 designs ahead of schedule, which is a good sign. It is also interesting to note that despite the fact that A14 lacks Super Power Rail backside power delivery (A12 will gain SPR in 2H 2019), it is set to be adopted not only by client processors, but also by AI/HPC applications.

“We are observing a strong level of customer interest and engagement on both smartphone and HPC/AI applications, and customer new tap-out activity is ongoing and ahead of schedule,” Wei said.

A14 is TSMC’s next-generation process technology that combines the company’s 2nd Generation GAA nanosheet transistors with a new standard-cell architecture to improve performance, power efficiency, and transistor density. Compared with N2, TSMC expects A14 to deliver a 10% – 15% performance uplift at the same power and transistor count, or reduce power consumption by 25%–30% at the same frequency and complexity. The node is also projected to increase transistor density by around 20% for mixed designs and by 23% for logic.