AVX-512 support is reportedly returning with Intel’s next-gen Nova Lake CPUs — Latest Linux kernel patches reveal P-cores and E-cores will gain native 512-bit execution
When Intel switched to a hybrid architecture with its 12th-Gen Alder Lake PUs, it removed AVX-512 support from the lineup entirely because the E-cores didn’t support it. Since then, every subsequent generation has shipped without it… until now. Just today, a new Linux patch pushed in the RAID optimized path has revealed that AVX-512 is finally returning to Intel CPUs with Nova Lake, present on both P-cores and E-cores.
Intel has been working toward a unified AVX solution for the past few years, as it was originally a champion of the SMID extensions before running into the hybrid hurdle with Alder Lake. Getting past that hurdle is AVX10, which Intel first detailed a few years back. With AVX10.2, 512-bit instructions will run on the P-cores, while either core type can handle converged 256-bit instructions.
As such, the E-cores would have their processing width capped at 256-bit, while the P-cores would be open to the full 512-bit wide pipelines. Any thread could swiftly move between either core type with AVX10 implemented. Previously, if the scheduler shifted a 512-bit task running on a P-core to an E-core, the application would crash instantly because those E-cores couldn’t process the instruction.
However, the new patches suggest that Intel has now mandated native 512-bit execution across both P-cores and E-cores, no longer requiring the latter to step down and process the data a bit slower. This is a major development over the standard we originally expected Intel to adopt; the E-cores are apparently becoming just as performant as the P-cores when it comes to SIMD instructions with Nova Lake and later.
Intel’s original announcement showed that it had already uncoupled the software improvements of AVX-512 from the physical width of the register, so the new instruction features could remain present for both 512-bit and 256-bit execution. This includes things like masking, embedded broadcast for rounding math operations, and doubling the number of the registers themselves from 16 to 32.
It remains unclear if we will ever see this version of AVX10 on client CPUs, as it seems Nova Lake is going purely for 512-bit execution across both core types. AMD’s current-gen Zen 5 processors also have full 512-bit wide registers, while the previous Zen 4 architecture divided a single 512-bit task across two 256-bit execution units over two clock cycles. This ensured execution remained disruption-free even if it took longer.
The last time we saw native AVX-512 support on an Intel client family was Rocket Lake (11th Gen), right before the hybrid era ushered in by Alder Lake. For modern AI workloads and other compute-heavy tasks such as encoding or simulations, AVX-512 instructions bring a huge performance benefit that’s foolish to be left on the table. Keep in mind that this is just a Linux patch at the moment and that Intel hasn’t officially announced native AVX-512 support for Nova Lake yet.
